In semiconductor processing, the wafer size continues to increase and the integrated circuit feature size continues to decrease. Further increases wafer size and further decreases in feature size require improvements in thermal process control. The temperature at which wafers are processed has a first-order influence on the diffusion, deposition, and other thermal processes. Batch furnaces continue to play a significant role for thermal processing because of their large batch size and correspondingly low cost per processed wafer. A target in batch thermal processing is to achieve improved temperature control while maintaining high equipment utilization and large wafer batch sizes. The requirements of high-quality temperature control include a high ramp rate with good temperature uniformity during the ramp, fast temperature stabilization with little or no temperature overshoot, smaller steady-state temperature error band, shorter downtime for controller parameter tuning, etc. The traditional single-loop Proportional-Integral-Derivative (PID) controllers cannot achieve the required temperature control performance. PID controllers with cascade or nested control loops have been used in attempts to provide improved temperature control. However, these and other previous approaches have practical drawbacks related to complexity and computational requirements.